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High Speed, 12 V, Synchronous Power MOSFET Driver
POWER MANAGEMENT Description
The SC1210 is a high speed, dual output driver designed to drive high-side and low-side MOSFETs in a synchronous Buck converter. These drivers can work with many Semtech PWM controllers to provide a cost effective multi-phase voltage regulator for advanced microprocessors. A 30ns max propagation delay from input transition to the gate of the power FET's guarantees operation at high switching frequencies. Internal overlap protection circuit prevents shoot-through from Vin to PGND in the main and synchronous MOSFETs. The adaptive overlap protection circuit ensures the bottom FET does not turn on until the top FET source has reached 1V, to prevent crossconduction. 8.5V gate drive provides optimum enhancement of MOSFETs at minimum driver and MOSFET switching loss. High current drive capability allows fast switching, thus reducing switching losses at high (up to 1.5MHz) frequencies without causing thermal stress on the driver. Under-voltage-lockout and over-temperature shutdown features are included for proper protection and safe operation. Timed latches and improved robustness are built into the safty functions such as the Under Voltage Lockout and adaptive Shoot-through protection circuitry to prevent false triggering. The SC1210 is offered in a standard SO-8 package.
SC1210
Features
u High efficiency u +12V supply voltage with internal LDO for optimum
gate drive
u High peak drive current u Adaptive non-overlapping gate drives provide u u u u u u u
shoot-through protection Fast rise and fall times (15ns typical with 3000pf load) Ultra-low (<30ns) propagation delay (BG going low) Floating top gate drive Crowbar function for over voltage protection High frequency (to 1.5 MHz) operation allows use of small inductors and low cost ceramic capacitors Under-voltage-lockout Low quiescent current
Applications
u Intel PentiumTM processor power supplies u AMD AthlonTM and K8TM processor power supplies u High current low voltage DC-DC converters
Typical Application Circuit
Vin (+12V)
R3 2R2 R1 C1 1uF 1 2 3 4 D1 1N4148 SC1210 C2 1uF C3 1uF DRN TG BST CO U1 PGND BG VREG VIN 8 7 6 5 1R0
Q1
C4 10uF
1 R2 1R0 C6 2.2nF
L1
Vout 2
PWM
Q2
C5
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SC1210
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Parameter VI N Supply Voltage BST to DRN BST to PGND BST to PGND Pulse DRN to PGND DRN to PGND Pulse PWM Input Thermal Resistance Junction to Case Operating Junction Temperature Range Storage Temperature Range Lead Temperature (Soldering) 10 Sec.
Symbol VI N VBST-DRN VBST-PGND VBST-PULSE VDRN-PGND VDRN-PULSE CO JC TJ TSTG TLEAD
Conditions
Maximum 16 11 40
Units V V V V V V V C/W C C C
tPULSE < 100ns
45 -2 to 30
tPULSE < 200ns
-5 to 35 -0.3 to 8.5 40 0 to +125 -65 to +150 300
Electrical Characteristics
Unless specified: TA = 25C; VIN = 12V; VREG = 8.5V
Parameter Pow er Supply Supply Voltage Qui escent C urrent, Operati ng U nder Voltage Lockout Start Threshold of VREG Voltage Hysteresi s Internal LD O LD O Output D rop Out Voltage
Symbol
C onditions
Min
Typ
Max
U nits
VI N Iq_op
9
12 3.0
15
V mA
VREG_START VhysUVLO
4 160
4.3
V mV
VREG VDROP
VI N = 9V to 16V VI N = 5V to 8.8V
8.5 0.3
V V
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SC1210
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless specified: TA = 25C; VIN = 12V; VREG = 8.5V
Parameter CO Logic High Input Voltage Logic Low Input Voltage T hermal Shutdown Over Temperature Trip Point Hysteresis High Side Driver (T G) Output Impedance Rise Time Fall Time Propagation Delay, TG Going High Propagation Delay, TG Going Low Low-Side Driver (BG) Output Impedance Rise Time Fall Time Propagation Delay, BG Going High Propagation Delay, BG Going Low Under-Voltage-Lockout T ime Delay VREG ramping up VREG ramping down
Symbol
Conditions
Min
Typ
Max
Units
VCO_H VCO_L
2.0 0.8
V V
TOTP THYST
155 10
C C
RSRC_TG RSINK_TG tR_TG tF_TG tPDH_TG tPDL_TG
1.5 VBST - VDRN = 8.5V CL = 3nF, VBST - VDRN = 8.5V CL = 3nF, VBST - VDRN = 8.5V VBST - VDRN = 8.5V VBST - VDRN = 8.5V 1.0 15 10 37 30
3.0 2.0
ns ns ns ns
RSRC_BG RSINK_BG tR_BG tF_BG tPDH_BG tPDL_BG
VBST - VDRN = 8.5V CL = 3nF, VBST - VDRN = 8.5V CL = 3nF, VBST - VDRN = 8.5V VBST - VDRN = 8.5V VBST - VDRN = 8.5V
1.5 1.5 10 10 20 27
3.0 3.0
ns ns ns ns
tPDH_UVLO tPDL_UVLO
2 2
s s
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SC1210
POWER MANAGEMENT Timing Diagrams
CO
DRN
1.0V
TG tPDH_TG tR_TG tPDL_TG tF_TG
BG tPDL_BG tF_BG
1.4V
tPDH_BG
tR_BG
Rising Edge Transition
Falling Edge Transition
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SC1210
POWER MANAGEMENT Pin Configuration
Top View
Ordering Information
Device
(1)
P ackag e SO-8
Temp Range (TJ) 0 to 125C
SC1210STR
DRN TG BST CO
1 2 3 4
(SO-8)
8 7 6 5
PGND BG VREG VIN
Note: (1) Only available in tape and reel packaging. A reel contains 2500 devices.
Pin Descriptions
Pin # 1 2 3 4 5 6 7 8 Pin N ame D RN TG BST CO VIN VREG BG PGND Pin Function The drai n node of the low-si de MOSFET (or swi tchi ng node) of the synchronous buck converter. Output gate dri ve for the swi tchi ng (top) MOSFET. Bootstrap pi n. A capaci tor i s connected between BST and D RN pi ns to develop the floati ng bootstrap voltage for the hi gh-si de MOSFET. The capaci tor value i s typi cally 1F (cerami c). Logi c level PWM i nput si gnal to the SC 1210 suppli ed by external controller. An i nternal 50kohm resi stor i s connected from thi s pi n to PGND . Supply power for LD O. C onnect to i nput power rai l of the converter. LD O output. D ecouple wi th 1F to 4.7F (cerami c) wi th lead length no more than 0.2" (5mm). Output gate dri ve for the synchronous (bottom) MOSFET. Ground. Keep thi s pi n close to the synchronous MOSFETs source.
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SC1210
POWER MANAGEMENT Block Diagram
VIN
LDO
VREG
UVLO BST TG CONTROL & OVERLAP PROT ECTION CIRCUIT DRN
CO
PGND
BG
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SC1210
POWER MANAGEMENT Applications Information
THEORY OPERATION THEOR Y OF OPERATION The SC1210 is a high speed, dual output driver designed to drive top and bottom MOSFETs in a synchronous Buck converter. It features adaptive delay for shoot-through protection, VID-on-Fly operation, and internal LDO for optimum gate drive voltage. These drivers combined with variety of Semtech PWM controllers form multi-phase voltage regulators for advanced microprocessors. UVLO A supply voltage has to be applied to VIN pin of the SC1210. The top and bottom gates are held low until VIN exceeds UVLO threshold of the driver. Then the top gate remains low and the bottom gate is pulled high to turn on the bottom FET. Gate Transition Shoot Through Pro Gat e Transition and Shoo t Thr ough Pr o t ection Refer to the timing diagrams section, the rising edge of the PWM input initiates the bottom FET turn-off and the top FET turn-on. After a short propagation delay (tPDL_BG), the bottom gate begins to fall (tF_BG). An adaptive circuit in the SC1210 monitors the bottom gate voltage to drop below 1.4V. Then after a preset delay time (tPDH_TG) is expired, the top gate turns on. The delay time is set to be 20ns typically. This prevents the top FET from turning on until the bottom FET is off. During the transition, the inductor current is freewheeling through the body diode of either bottom FET or top FET, upon the direction of the inductor current. The phase node could be low (ground) or high (VIN). The falling edge of the PWM input controls the top FET turn-off and the bottom FET turn-on. After a short propagation delay (tPDL_TG), the top gate begins to fall (tF_TG). As the inductor current is commutated from the top FET to the body diode of the bottom FET, the phase node begins to fall. The adaptive circuit in the SC1210 detects the phase node voltage. It holds the bottom FET off until the phase node voltage has dropped below 1.0V. This prevents the top and bottom FETs from conducting simultaneously or shoot-through. VID-on-Fly Operation Certain new processors have required to changing the VID dynamically during the operation, or refered as VIDon-Fly operation. A VID-on-Fly can occur under light load
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or heavy load conditions. At light load, it could force the converter to sink current. Upon turn-off of the top FET, the reversed inductor current has to be freewheeling through the body diode of the top FET instead of the bottom FET. As a result, the phase node voltage remains high. The SC1210 incorporates the ability by pulling the bottom gate to high internally, which over rides the adaptive circuit and turns the bottom FET on. The delay time from the PWM falling egde to the bottom gate turn-on is set at 200ns typically. Gate Drive Voltage Optimized Gat e Driv e Voltage With the supply voltage in between 9V to 16V, an internal LDO is designed with the SC1210 to bring the voltage to a lower level for gate drive. An external Ceramic capacitor(1uF to 4.7uF) connected in between Vreg to ground is needed to decouple the LDO. The LDO output powers up the low gate driver, and the high gate drive is powered by the external bootstrap circuit. The LDO output voltage is set at 8.5V. The manufacture data and bench tested results show that, for low Rdson FETs run at applied load current, the optimum gate drive voltage is around 8.5V, where the total power losses of power FETs, including conduction loss, switching loss, and the gate drive loss, are minimized. Thermal Shut Down The SC1210 will shut down by pulling both driver outputs low if its junction temperature, Tj, exceeds 155C. COMPONENT SELECTION Bootstrap Circuit The SC1210 uses an external bootstrap circuit to provide a voltage for the top FET drive. This voltage, referring to the Phase Node, is held up by a bootstrap capacitor. Typically, it is recommended to use a 1uF ceramic capacitor with 25V rating and a commonly available diode IN4148 for the bootstrap circuit. In addition, a small resistor may be added in between DRN of the SC1210 and the Phase Node. The resistor is used to allievate the stress of the SC1210 from exposing to the negative spike on the DRN pin. A negative spike could occur at
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SC1210
POWER MANAGEMENT Applications Information (Cont.)
the Phase Node during the top FET turn-off due to parasitic inductance in the switching loop. The spike could be minimized with a careful PCB layout. In those applications with TO-220 package FETs, it is recommended to use a clamping diode on the DRN pin to mitigate the impact of the excessive phase node negative spike. Filters for Supply Power For VREG pin of the SC1210, it is recommended to use a 1uF to 4.7uF, 25V rating ceramic capacitor for decoupling. LAY LAY OUT GUIDELINES The switching regulator is a high di/dt power circuit. Its Printed Circuit Board (PCB) layout is critical. A good layout can achieve an optimum circuit performance while minimized the component stress, resulting in better system reliability. For a multi-phase voltage regulator, the SC1210 driver, FETs, inductor, and supply decoupling capacitors in each phase have to be considered to yield a proper PCB layout. For the SC1210 driver, the following guidelines are typically recommended during PCB layout: 1. Place the SC1210 close to the FETs for shortest gate drive traces and ground return paths. 2. Connect bypass capacitors as close as possible to decoupling pins (VREG and VIN) and PGND. The trace length of the decoupling capacitor on VREG pin should be no more than 0.2" (5mm). 3. Locate the components of the bootstrap circuit close to the SC1210. 4. Provide a proper decoupling for the FETs to reduce the inductive kick seen by the DRN pin.
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SC1210
POWER MANAGEMENT Outline Drawing Power Outline Drawing - -SOIC-8 SOIC-8
Land Pattern - SOIC-8
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Rd., Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
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